Filter
Top Products
Contents
Preface..............................................................................................................................11
1Introduction.............................................................................................................13
1.1Overview.....................................................................................................................14
1.2ARMSubsysteminTMS320DM646xDMSoC.........................................................................14
2ARMSubsystemOverview.........................................................................................15
2.1PurposeoftheARMSubsystem.........................................................................................16
2.2ComponentsoftheARMSubsystem....................................................................................16
2.3References..................................................................................................................17
3ARMCore................................................................................................................19
3.1Introduction..................................................................................................................20
3.2OperatingStates/Modes...................................................................................................21
3.3ProcessorStatusRegisters...............................................................................................21
3.4ExceptionsandExceptionVectors.......................................................................................22
3.5The16-BIS/32-BISConcept..............................................................................................23
3.5.116-BIS/32-BISAdvantages......................................................................................23
3.6Co-Processor15(CP15)..................................................................................................24
3.6.1AddressesinanARM926EJ-SSystem........................................................................24
3.6.2MemoryManagementUnit(MMU)..............................................................................24
3.6.3CachesandWriteBuffer........................................................................................25
3.7Tightly-CoupledMemory..................................................................................................26
4SystemMemory.......................................................................................................29
4.1MemoryMap................................................................................................................30
4.1.1ARMInternalMemories..........................................................................................30
4.1.2ExternalMemories................................................................................................30
4.1.3DSPMemories.....................................................................................................30
4.1.4Peripherals.........................................................................................................30
4.2MemoryInterfacesOverview.............................................................................................31
4.2.1DDR2MemoryController........................................................................................31
4.2.2ExternalMemoryInterface.......................................................................................31
5PLLController..........................................................................................................35
5.1PLLModule.................................................................................................................36
5.2PLL1Control................................................................................................................38
5.2.1DeviceClockGeneration.........................................................................................39
5.2.2StepsforChangingPLL1/CoreDomainFrequency..........................................................39
5.3PLL2Control................................................................................................................41
5.3.1DeviceClockGeneration.........................................................................................42
5.3.2StepsforChangingPLL2Frequency...........................................................................42
5.4PLLControllerRegisterMap..............................................................................................45
5.4.1PeripheralIDRegister(PID).....................................................................................46
5.4.2ResetTypeStatusRegister(RSTYPE)........................................................................46
SPRUEP9A–May2008Contents3
SubmitDocumentationFeedback