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6.6.10PowerDomainControlRegister(PDCTL0)
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PSCRegisters
Thepowerdomaincontrolregister(PDCTL0)isshowninFigure6-12anddescribedinTable6-16.
Figure6-12.PowerDomainControlRegister(PDCTL0)
3116
Reserved
R-0
151098710
ReservedReservedReservedNEXT
R-0R/W-0R/W-0R-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table6-16.PowerDomainControlRegister(PDCTL0)FieldDescriptions
BitFieldValueDescription
31-10Reserved0Reserved
9-8Reserved0Reserved.Alwayswrite0tothesebits.
7-1Reserved0Reserved
0NEXTPowerdomainnextstate.IntheDM646xDMSoC,thereisonlyonepowerdomain(AlwaysOn).The
AlwaysOnpowerdomainisalwaysintheONstatewhenthechipispowered-on.Thisfieldhasno
effect.
0Powerdomainoff.
1Powerdomainon.
SPRUEP9A–May2008PowerandSleepController(PSC)75
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