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5.2.1DeviceClockGeneration
5.2.2StepsforChangingPLL1/CoreDomainFrequency
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PLL1Control
PLLC1generatesseveralclocksfromthePLL1outputclockforusebythevariousprocessorsand
modules.ThesearesummarizedinTable5-1.
Note:OntheDM646xDMSoC,allPLL1SYSCLKndividersareprogrammablebutyoushouldnot
changethedividervaluetomaintaintheclockratiosbetweenvariousmodulesofthedevice.
Youshouldonlyusethepower-updefaultdividervaluesforallPLL1SYSCLKndividersfor
normaldeviceoperation.
PLL2SYSCLK1dividervalueisprogrammableandyoumaychangethedividervalueforthe
desiredDDR2memorycontrollerclockfrequency.
Table5-1.PLLC1OutputClocks
OutputClockDefaultDividerDividerTypeUsedby
SYSCLK1/1ProgrammableDSPSubsystem
SYSCLK2/2ProgrammableARMSubsystem,EDMA,HDVICPs,DDR2Memory
Controller,PCI,VPIFs,TSIFs,VDCE
SYSCLK3/4ProgrammableHPI,EMIFA,USB,VLYNQ,UARTs,McASPs,I2C,SPIs,
PWMs,Timers,GPIO,EMAC,CRGEN,SystemModule
SYSCLK4/6ProgrammableATA
SYSCLK5/8ProgrammableTSIF1
SYSCLK6/8ProgrammableTSIF2
SYSCLK8/8ProgrammableVPIF2
SYSCLK9/6ProgrammableVLYNQ
SYSCLKBPDEV_CLKIN/nProgrammableTSIFs
AUXCLKDEV_CLKINFixedat27MHZTSIFs,VPIFs
RefertotheappropriatesubsectiononhowtoprogramthePLL1/CoreDomainclocks:
•IfthePLLispowereddown(PLLPWRDNbitinPLLCTLissetto1),followthefullPLLinitialization
procedureinSection5.2.2.1toinitializethePLL.
•IfthePLLisnotpowereddown(PLLPWRDNbitinPLLCTLisclearedto0),followthesequencein
Section5.2.2.2tochangethePLLmultiplier.
•IfthePLLisalreadyrunningatadesiredmultiplierandonlytheSYSCLKdividersneedtobechanged,
followthesequenceinSection5.3.2.4.
NotethatthePLLispowereddownafterthefollowingdevice-levelglobalresets:
•Power-onReset(POR)
•WarmReset(RESET)
•MaxReset
SPRUEP9A–May2008PLLController39
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