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8.4.1FastInterruptRequestStatusRegister0(FIQ0)
8.4.2FastInterruptRequestStatusRegister1(FIQ1)
AINTCRegisters
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Thefastinterruptrequeststatusregister0(FIQ0)isshowninFigure8-5anddescribedinTable8-3.
InterruptstatusofINT[31:0](ifmappedtoFIQ).
Figure8-5.FastInterruptRequestStatusRegister0(FIQ0)
3116
FIQ
R/W-1
150
FIQ
R/W-1
LEGEND:R/W=Read/Write;-n=valueafterreset
Table8-3.FastInterruptRequestStatusRegister0(FIQ0)FieldDescriptions
BitFieldValueDescription
31-0FIQ[n]InterruptstatusofINTn,ifmappedtofastinterruptrequest(FIQ31-0).
0Whenreadingbit,interruptoccurred.
1Whenwritingbit,acknowledgeinterrupt.
Thefastinterruptrequeststatusregister1(FIQ1)isshowninFigure8-6anddescribedinTable8-4.
InterruptstatusofINT[63:32](ifmappedtoFIQ).
Figure8-6.FastInterruptRequestStatusRegister1(FIQ1)
3116
Reserved
R-1
150
FIQ
R/W-1
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table8-4.FastInterruptRequestStatusRegister1(FIQ1)FieldDescriptions
BitFieldValueDescription
31-16Reserved1Reserved
15-0FIQ[n]InterruptstatusofINTn,ifmappedtofastinterruptrequest(FIQ47-32).
0Whenreadingbit,interruptoccurred.
1Whenwritingbit,acknowledgeinterrupt.
ARMInterruptController(AINTC) 92SPRUEP9A–May2008
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