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3.6Co-Processor15(CP15)
3.6.1AddressesinanARM926EJ-SSystem
3.6.2MemoryManagementUnit(MMU)
Co-Processor15(CP15)
www.ti.com
Thesystemcontrolcoprocessor(CP15)isusedtoconfigureandcontrolinstructionanddatacaches,
Tightly-CoupledMemories(TCMs),MemoryManagementUnits(MMUs),andmanysystemfunctions.The
CP15registersareonlyaccessiblewithMRCandMCRinstructionsbytheARMinaprivilegedmodelike
supervisormodeorsystemmode.
ThreedifferenttypesofaddressesexistinanARM926EJ-Ssystem.Theyareasfollows:
Table3-2.DifferentAddressTypesinARMSystem
DomainARM9EJ-SCachesandMMUTCMandAMBABus
AddresstypeVirtualAddress(VA)ModifiedVirtualAddress(MVA)PhysicalAddress(PA)
AnexampleoftheaddressmanipulationthatoccurswhentheARM9EJ-Scorerequestsaninstructionis
showninExample3-1
Example3-1.AddressManipulation
TheVAoftheinstructionisissuedbytheARM9EJ-Score.
TheVAistranslatedtotheMVA.TheInstructionCache(Icache)andMemoryManagementUnit(MMU)
detecttheMVA.
IftheprotectioncheckcarriedoutbytheMMUontheMVAdoesnotabortandtheMVAtagisinthe
Icache,theinstructiondataisreturnedtotheARM9EJ-Score.
IftheprotectioncheckcarriedoutbytheMMUontheMVAdoesnotabort,andtheMVAtagisnotin
thecache,thentheMMUtranslatestheMVAtoproducethePA.
Note:SeeChapter2oftheProgrammersModeloftheARM926EJ-STRM,downloadablefrom
http://www.arm.com/arm/TRMsformoredetailedinformation.
TheARM926EJ-SMMUprovidesvirtualmemoryfeaturesrequiredbyoperatingsystemssuchas
SymbianOS,WindowsCE,andLinux.Asinglesetoftwolevelpagetablesstoredinmainmemorycontrols
theaddresstranslation,permissionchecks,andmemoryregionattributesforbothdataandinstruction
accesses.TheMMUusesasingleunifiedTranslationLookasideBuffer(TLB)tocachetheinformation
heldinthepagetables.
TheMMUfeaturesareasfollows:
•StandardARMarchitecturev4andv5MMUmappingsizes,domains,andaccessprotectionscheme.
•Mappingsizesare1MB(sections),64KB(largepages),4KB(smallpages)and1KB(tinypages)
•Accesspermissionsforlargepagesandsmallpagescanbespecifiedseparatelyforeachquarterof
thepage(subpagepermissions)
•Hardwarepagetablewalks
•InvalidateentireTLB,usingCP15register8
•InvalidateTLBentry,selectedbyMVA,usingCP15register8
•LockdownofTLBentries,usingCP15register10
Note:SeeChapter3oftheMemoryManagementUnitoftheARM926EJ-STRM,downloadable
fromhttp://www.arm.com/arm/TRMsformoredetailedinformation.
ARMCore 24SPRUEP9A–May2008
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