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8.4.7InterruptEnableRegister0(EINT0)
8.4.8InterruptEnableRegister1(EINT1)
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AINTCRegisters
Theinterruptenableregister0(EINT0)isshowninFigure8-11anddescribedinTable8-9.
Figure8-11.InterruptEnableRegister0(EINT0)
3116
EINT
R/W-0
1510
EINTEINT0
R/W-0R-1
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table8-9.InterruptEnableRegister0(EINT0)FieldDescriptions
BitFieldValueDescription
31-1EINT[n]InterruptenableforINTn.Bits1through31representinterrupts1-31,respectively.
0Interruptisdisabled.
1Interruptisenabled.
0EINT01Interrupt0isnonmaskableandisalwaysenabled.
Theinterruptenableregister1(EINT1)isshowninFigure8-12anddescribedinTable8-10.
Figure8-12.InterruptEnableRegister1(EINT1)
3116
Reserved
R-0
150
EINT
R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table8-10.InterruptEnableRegister1(EINT1)FieldDescriptions
BitFieldValueDescription
31-16Reserved0Reserved
15-0EINT[n]InterruptenableforINTn.Bits0through15representinterrupts32-47,respectively.
0Interruptisdisabled.
1Interruptisenabled.
SPRUEP9A–May2008ARMInterruptController(AINTC)95
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