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5.3.2.3ChangingPLLMultiplier
5.3.2.4ChangingSYSCLKDividers
PLL2Control
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IfthePLLisnotpowereddown(PLLPWRDNbitinPLLCTLisclearedto0)andthePLLstabilizationtime
ispreviouslymet(step7inSection5.3.2.2),followthisproceduretochangePLL2multiplier.
1.BeforechangingthePLLfrequency,switchtoPLLbypassmode:
a.ClearthePLLENSRCbitinPLLCTLto0toallowPLLCTL.PLLENtotakeeffect.
b.ClearthePLLENbitinPLLCTLto0(selectPLLbypassmode).
c.Waitfor20MXIclockcyclestoensurePLLCswitchestobypassmodeproperly.
2.SetthePLLRSTbitinPLLCTLto1(resetPLL).
3.ClearthePLLDISbitinPLLCTLto0(enablethePLL)toallowPLLoutputstostarttoggling.Notethat
thePLLCisstillatPLLbypassmode;therefore,thetogglingPLLoutputdoesnotgetpropagatedto
therestofthedevice.
4.ProgramtherequiredmultipliervalueinthePLLmultipliercontrolregister(PLLM).
5.Ifnecessary,programthePLLcontrollerdivider1register(PLLDIV1)tochangetheSYSCLK1divide
value:
a.ProgramtheRATIOfieldinPLLDIV1withthedesireddividefactor.
b.SettheGOSETbitinPLLCMDto1toinitiateanewdividertransition.
c.WaitfortheGOSTATbitinthePLLcontrollerstatusregister(PLLSTAT)toclearto0(completionof
phasealignment).
6.WaitforPLLtoresetproperly.ThePLLresettimeisaminimumof32MXIclockcycles.
7.ClearthePLLRSTbitinPLLCTLto0tobringthePLLoutofreset.
8.Waitfor2000MXIclockorreferenceclockcyclestoallowPLLtolock.
9.SetthePLLENbitinPLLCTLto1toremovethePLLfrombypassmode.
ThissectiondiscussesthesoftwaresequencetochangetheSYSCLKdividers.TheSYSCLKdivider
changesequenceisalsoreferredtoasGOoperation,asitinvolveshittingtheGObit(GOSETbitin
PLLCMD)toinitiatethedividerchange.
1.CheckfortheGOSTATbitinthePLLcontrollerstatusregister(PLLSTAT)toclearto0toindicatethat
noGOoperationiscurrentlyinprogress.
2.ProgramtheRATIOfieldinthePLLcontrollerdivider1register(PLLDIV1)withthedesireddivide
factor.
3.SettheGOSETbitinPLLCMDto1toinitiateanewdividertransition.
4.WaitfortheGOSTATbitinPLLSTATtoclearto0(completionofdividerchange).
Note:OntheDM646xDMSoC,allPLL1SYSCLKndividersareprogrammablebutyoushouldnot
changethedividervaluetomaintaintheclockratiosbetweenvariousmodulesofthedevice.
Youshouldonlyusethepower-updefaultdividervaluesforallPLL1SYSCLKndividersfor
normaldeviceoperation.
PLL2SYSCLK1dividervalueisprogrammableandyoumaychangethedividervalueforthe
desiredDDR2memorycontrollerclockfrequency.
44PLLControllerSPRUEP9A–May2008
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