Filter
Top Products
5.3.1DeviceClockGeneration
5.3.2StepsforChangingPLL2Frequency
5.3.2.1DDR2MemoryControllerConsiderationsWhenModifyingPLL2Frequency
5.3.2.1.1PLL2FrequencyChangeStepsWhenDDR2MemoryControllerisInReset
PLL2Control
www.ti.com
PLLC2generatestheclockfromthePLL2outputclockforusebytheDDR2memorycontroller,asshown
inTable5-2.
TheSYSCLK1outputclockdividervaluedefaultsto/1,resultingina594-MHZDDRPhyclock(297-MHZ
DDR).Itcanbemodifiedbysoftware(usingtheRATIObitinPLLDIV1)incombinationwithotherPLL
multiplierstoachievethedesiredDDR2memorycontrollerclockrate.
Table5-2.PLLC2OutputClock
OutputClockDefaultDividerDividerTypeUsedby
SYSCLK1/1ProgrammableDSPSubsystem
ThePLLC2isprogrammedsimilarlytothePLLC1.Refertotheappropriatesubsectiononhowtoprogram
thePLL2clocks:
•IfthePLLispowereddown(PLLPWRDNbitinPLLCTLissetto1),followthefullPLLinitialization
procedureinSection5.3.2.2toinitializethePLL.
•IfthePLLisnotpowereddown(PLLPWRDNbitinPLLCTLisclearedto0),followthesequencein
Section5.3.2.3tochangethePLLmultiplier.
•IfthePLLisalreadyrunningatadesiredmultiplierandonlytheSYSCLKdividerneedstobechanged,
followthesequenceinSection5.3.2.4.
NotethatthePLLispowereddownafterthefollowingdevice-levelglobalresets:
•Power-onReset(POR)
•WarmReset(RESET)
•MaxReset
Inaddition,notethatthePLL2frequencydirectlyaffectstheDDR2memorycontroller.TheDDR2memory
controllerrequiresaspecialsequencetobefollowedbeforeandafterchangingthePLL2frequency.
FollowtheadditionalconsiderationsfortheDDR2memorycontrollerinSection5.3.2.1,inordertonot
corruptDDR2memorycontrolleroperation.
BeforechangingPLL2and/orPLLC2frequency,taketheDDR2memorycontrollerrequirementsinto
account.IftheDDR2memorycontrollerisusedinthesystem,followtheadditionalstepsinthissectionto
changePLL2and/orPLLC2frequencywithoutcorruptingDDR2memorycontrolleroperation.
•IftheDDR2memorycontrollerisinresetwhenyoudesiretochangethePLL2frequency,followthe
stepsinSection5.3.2.1.1.
•IftheDDR2memorycontrollerisalreadyoutofresetwhenyoudesiretochangethePLL2frequency,
followthestepsinSection5.3.2.1.2.
ThissectiondiscussesthestepstochangethePLL2frequencywhentheDDR2memorycontrollerisin
reset.NotethattheDDR2memorycontrollerisinresetafterthesedevice-levelglobalresets:power-on
reset(POR),warmreset(RESET),andmaxreset.
1.LeavetheDDR2memorycontrollerinreset.
2.ProgramthePLL2clocksbyfollowingthestepsintheappropriatesection:Section5.3.2.2,
Section5.3.2.3,orSection5.3.2.4.(DiscussioninSection5.3.2explainswhichistheappropriate
subsection).
3.InitializetheDDR2memorycontroller.ThestepsforDDR2memorycontrollerinitializationarefoundin
theTMS320DM646xDMSoCDDR2MemoryControllerUser'sGuide(SPRUEQ4).
PLLController 42SPRUEP9A–May2008
SubmitDocumentationFeedback