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5.4.6PLLControllerDivider2Register(PLLDIV2)
PLLControllerRegisterMap
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ThePLLcontrollerdivider2register(PLLDIV2)isshowninFigure5-9anddescribedinTable5-10.
Divider2controlsthedividerforSYSCLK2.PLLDIV2isnotusedonPLL2.
Note:OntheDM646xDMSoC,allPLL1SYSCLKndividersareprogrammablebutyoushouldnot
changethedividervaluetomaintaintheclockratiosbetweenvariousmodulesofthedevice.
Youshouldonlyusethepower-updefaultdividervaluesforallPLL1SYSCLKndividersfor
normaldeviceoperation.
Figure5-9.PLLControllerDivider2Register(PLLDIV2)
3116
Reserved
R-0
1514430
D2ENReservedRATIO
R/W-1R-0R/W-1
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table5-10.PLLControllerDivider2Register(PLLDIV2)FieldDescriptions
BitFieldValueDescription
31-16Reserved0Reserved
15D2ENDividerenableforSYSCLK2.
0Disable
1Enable
14-4Reserved0Reserved
3-0RATIO0-FhDividerratio.DividerValue=RATIO+1.RATIOdefaultsto1(PLL1divideby2).
PLLController 50SPRUEP9A–May2008
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