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4.1MemoryMap
4.1.1ARMInternalMemories
4.1.2ExternalMemories
4.1.3DSPMemories
4.1.4Peripherals
MemoryMap
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TheTMS320DM646xDMSoChasmultipleon-chipmemoriesassociatedwithitstwoprocessorsand
varioussubsystems.Tohelpsimplifysoftwaredevelopment,aunifiedmemorymapisusedwhere
possibletomaintainaconsistentviewofdeviceresourcesacrossallbusmasters.
Fordetailedmemory-mapinformation,seethedevice-specificdatamanual.
TheARMhasaccesstothefollowingARMinternalmemories:
•32KBARMInternalRAMonTCMinterface,logicallyseparatedintotwo16-KBpagestoallow
simultaneousaccessonanygivencycle,ifthereareseparateaccessesforcode(I-TCMbus)anddata
(D-TCM)tothedifferentmemoryregions.
•8KBARMInternalROM
TheARMhasaccesstothefollowingexternalmemories:
•DDR2synchronousDRAM
•AsynchronousEMIF/NOR/NANDFlash
•ATA
ThesememoryinterfacesaredescribedinSection1.1.
Fordocumentationrelatedtotheseinterfaces,seetheRelatedDocumentationsectionatthebeginningof
thisdocument.
TheARMhasaccesstothefollowingDSPmemories:
•L2RAM(Level2RAM)
•L1PRAM(Level1ProgramRAM)
•L1DRAM(Level1DataRAM)
TheARMhasaccesstothefollowingperipherals:
•AsynchronousEMIF(EMIFA)
•ATAController
•2ClockReferenceGenerators(CRGEN)
•DDR2MemoryController
•EnhancedDMA(EDMA)Controller
•EthernetMediaAccessController(EMAC)
•General-PurposeInput/Output(GPIO)
•HostPortInterface(HPI)
•Inter-ICCommunication(I2C)
•2MultichannelAudioSerialPorts(McASP)
•PeripheralComponentInterface(PCI)
•2PulseWidthModulators(PWM)
•SerialPortInterface(SPI)upto40MHZwith2chipselects
•2timersthatareconfigurableastwo64-bitorfour32-bittimersandone64-bitwatchdogtimer
•TransportStreamInterface(TSIF)
30SystemMemorySPRUEP9A–May2008
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