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4.2MemoryInterfacesOverview
4.2.1DDR2MemoryController
4.2.2ExternalMemoryInterface
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MemoryInterfacesOverview
•3UniversalAsynchronousReceiver/Transmitters(UART)(onewithmodemcontrol)
•UniversalSerialBus(USB)Controller
•VideoDataConversionEngine(VDCE)
•VLYNQInterface
•2VideoPortInterfaces(VPIF)
TheARMSubsystemalsohasaccesstothefollowinginternalperipherals:
•SystemModule
•PLLControllers
•PowerSleepController(PSC)
•ARMInterruptController(AINTC)
ThissectiondescribesthedifferentmemoryinterfacesofDM646xDMSoC.TheDM646xDMSoCsupports
severalmemoryandexternaldeviceinterfaces,includingthefollowing:
•DDR2synchronousDRAM
•AsynchronousEMIF/NOR/NANDFlash
•ATA
TheDDR2memorycontrollerisadedicatedinterfacetoDDR2SDRAM.ItsupportsJESD79D-2A
standardcompliantDDR2SDRAMdevicesandcansupporteither16-bitor32-bitinterfaces.
DDR2SDRAMplaysakeyroleinaDM646xDMSoC-basedsystem.Suchasystemisexpectedtorequire
asignificantamountofhigh-speedexternalmemoryforthefollowing:
•Bufferinginputimagedatafromsensorsorvideosources
•Intermediatebufferingforprocessing/resizingofimagedatainthevideodataconversionengine
(VDCE)
•Videoprocessingdisplaybuffers
•Bufferingforintermediatedatawhileperformingvideoencodeanddecodefunctions
•StorageofexecutablefirmwareforboththeARMandDSP
TheDM646xDMSoCexternalmemoryinterface(EMIF)providesan8-bitor16-bitdatabus,anaddress
buswidthofupto24-bits,and4dedicatedchipselects,alongwithmemorycontrolsignals.Thesesignals
arestaticallymultiplexedbetweenfourparallelinterfacemodules.Theinterfacemodulesare:
•EMIFmodule-providingasynchronousEMIF(EMIFA)andNANDinterfaces
•ATA–providingATA/IDEdrivesupport
•PCI
•HPI
SomeofthecontrolsignalsareconfigurableasGPIOsignalsiftheyarenotrequiredbytheEMIFA,ATA,
PCI,andHPI.Seethedevice-specificdatamanualformoreinformationonpinmultiplexing.
Seethedevice-specificdatamanualformoredetailsonpin-muxing.
SPRUEP9A–May2008SystemMemory31
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