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3.1Introduction
Introduction
www.ti.com
ThischapterdescribestheARMcoreanditsassociatedmemories.TheARMcoreconsistsofthe
followingcomponents:
•ARM926EJ-S-32-bitRISCprocessor
•16-KBInstructioncache
•8-KBDatacache
•MemoryManagementUnit(MMU)
•CP15tocontrolMMU,cache,etc.
•Javaaccelerator
•ARMInternalMemory
–32KBbuilt-inRAM
–8KBbuilt-inROM(bootROM)
•EmbeddedTraceModuleandEmbeddedTraceBuffer(ETM/ETB)
•Features:
–Themainwritebufferhasa16-worddatabufferanda4-addressbuffer
–Supportfor32/16-bitinstructionsets
–Fixedlittleendianmemoryformat
–EnhancedDSPinstructions
TheARM926EJ-SprocessorisamemberoftheARM9familyofgeneral-purposemicroprocessors.The
ARM926EJ-Sprocessortargetsmulti-taskingapplicationswherefullmemorymanagement,high
performance,lowdiesize,andlowpowerareallimportant.
TheARM926EJ-Sprocessorsupportsthe32-bitARMandthe16-bitTHUMBinstructionsets,enabling
youtotradeoffbetweenhighperformanceandhighcodedensity.Thisincludesfeaturesforefficient
executionofJavabytecodesandprovidingJavaperformancesimilartoJustinTime(JIT)Javainterpreter
withoutassociatedcodeoverhead.
TheARM926EJ-SprocessorsupportstheARMdebugarchitectureandincludeslogictoassistinboth
hardwareandsoftwaredebugging.TheARM926EJ-SprocessorhasaHarvardarchitectureandprovides
acompletehighperformancesubsystem,includingthefollowing:
•AnARM926EJ-Sintegercore
•AMemoryManagementUnit(MMU)
•SeparateinstructionanddataAMBAAHBbusinterfaces
•SeparateinstructionanddataTCMinterfaces
TheARM926EJ-SprocessorimplementsARMarchitectureversion5TEJ.
TheARM926EJ-Scoreincludesnewsignalprocessingextensionstoenhance16-bitfixed-point
performanceusingasingle-cycle32×16multiply-accumulate(MAC)unit.TheARMSubsystemalsohas
32KBofinternalRAMand8KBofinternalROM,accessibleviatheI-TCMandD-TCMinterfacesthrough
anarbiter.ThesamearbiterprovidesaslaveDMAinterfacetotherestoftheDM646xDMSoC.
Furthermore,theARMhasDMAandCFGbusmasterportsviatheAHBinterface.
20ARMCoreSPRUEP9A–May2008
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