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5.4.3PLLControlRegister(PLLCTL)
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PLLControllerRegisterMap
ThePLLcontrolregister(PLLCTL)isshowninFigure5-6anddescribedinTable5-7.
Figure5-6.PLLControlRegister(PLLCTL)
3116
Reserved
R-0
159876543210
ReservedCLKMODEReservedPLLENSRCPLLDISPLLRSTRsvdPLLPWRDNPLLEN
R-0R/W-0R-3hR/W-1R/W-1R/W-0R-0R/W-1R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table5-7.PLLControlRegister(PLLCTL)FieldDescriptions
BitFieldValueDescription
31-9Reserved0Reserved
8CLKMODEReferenceClockSelection
0Internaloscillator
1CLKINsquarewave
7-6Reserved1Reserved
5PLLENSRC0ThisbitmustbeclearedbeforePLLENwillhaveanyeffect.
4PLLDISAssertsDISABLEtoPLLifsupported.
0PLLdisableisde-asserted.
1PLLdisableisasserted.
3PLLRSTAssertsRESETtoPLLifsupported.
0PLLresetisasserted.
1PLLresetisnotasserted.
2Reserved0Reserved
1PLLPWRDNPLLpower-down.
0PLLoperation
1PLLpower-down
0PLLENPLLmodeenable.
0Bypassmode
1PLLmode,notbypassed
SPRUEP9A–May2008PLLController47
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