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8.1Introduction
8.2InterruptMapping
Introduction
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TheTMS320DM646xDMSoCARMinterruptcontroller(AINTC)hasthefollowingfeatures:
•Supportsupto64interruptchannels(16externalchannels)
•Interruptmaskforeachchannel
•EachinterruptchannelismappabletoaFastInterruptRequest(FIQ)ortoanInterruptRequest(IRQ)
typeofinterrupt.
•Hardwareprioritizationofsimultaneousinterrupts
•Configurableinterruptpriority(2levelsofFIQand6levelsofIRQ)
•Configurableinterruptentrytable(FIQandIRQprioritytableentry)toreduceinterruptprocessingtime
TheARMcoresupportstwointerrupttypes:FIQandIRQ.SeetheARM926EJTechnicalReference
ManualfordetailedinformationabouttheARM’sFIQandIRQinterrupts.Eachinterruptchannelis
mappabletoanFIQortoanIRQtypeofinterrupt,andeachchannelcanbeenabledordisabled.The
AINTCsupportsuser-configurableinterrupt-priorityandinterruptentryaddresses.Entryaddresses
minimizethetimespentjumpingtointerruptserviceroutines(ISRs).Whenaninterruptoccurs,the
correspondinghighestpriorityISR’saddressisstoredintheAINTC’sENTRYregister.TheIRQorFIQ
interruptroutinecanreadtheENTRYregisterandjumptothecorrespondingISRdirectly.Thus,theARM
doesnotrequireasoftwaredispatchertodeterminetheassertedinterrupt.
TheARM926EJCPUcoresupports2directinterrupts:FIQandIRQ.TheARMinterruptcontroller(AINTC)
prioritizesupto64interruptrequestsfromvariousperipheralsandsubsystems,listedinTable8-1,and
interruptstheARMCPU.Eachinterruptisprogrammableforupto8prioritylevels(6levelsforIRQand2
levelsforFIQ).InterruptsatthesameprioritylevelareservicedinorderbytheARMinterruptnumber,
withthelowestnumberhavingthehighestpriority.
86ARMInterruptController(AINTC)SPRUEP9A–May2008
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