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10.4.4EMIFAConfiguration
10.4.4.1EMIFACS2BusWidthConfiguration
10.4.4.2EMIFATimingConfiguration
10.4.5PCIEnable(PCIEN)Operation
DefaultDeviceConfigurations
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TheCS2BWpindeterminesthedefaultwidthofthefirstEMIFAchipselectspace(EM_CS2).IfCS2BW=
0,thespacedefaultsto8-bitswide;ifCS2BW=1,thespacedefaultsto16-bitswide.Thisallowsthe
ARMtomakefulluseofthewidthoftheattachedmemorydevice,ifbootingfromEMIFAorNAND.
Note:CS2BWonlyselectsthedefaultwidthandneedstobesetdependingonwhether8-bitor
16-bitEMIFAmemoryorNANDisusedatboottime.Afterboot,thewidthofCS2BWcanbe
changedbysoftwarebyaccessingtheappropriateEMIFAcontrolregister.
TheCS2BWinputaffectsonlythefirstEMIFAchipselectspace(EM_CS2).Allotherchipselectspaces
defaultto8-bitswideandmustbemodifiedusingtheappropriateEMIFAcontrolregisterif16-bitoperation
isdesired.
SeetheTMS320DM646xDMSoCAsynchronousExternalMemoryInterface(EMIF)User'sGuide
(SPRUEQ7)formoreinformationontheEMIF.
WhenEMIFAisenabled,thewaitstateregistersareresettotheslowestpossibleconfiguration,whichis
88cyclesperaccess(16cyclesofsetup,64cyclesofstrobe,and8cyclesofhold).Thus,witha27-MHz
clockatMXI,theEMIFAisconfiguredtorunat4.5MHz/88,whichequalsapproximately51kHzby
default.SeetheTMS320DM646xDMSoCAsynchronousExternalMemoryInterface(EMIF)User'sGuide
(SPRUEQ7)formoreinformationontheEMIF.
ThePCIENislatchedintothebootconfigurationregister(BOOTCFG)intheSystemModulefromthe
PCIENconfigurationpinattheendofreset(thatis,risingedgeofRESETorPOR).
ThePCIENconfigurationsignalisusedtoselectthedefaultconfigurationoftheHPI/PCI/EMIFApinsat
reset.ThisallowstheDM646xDMSoCtobePCI-compliantatresetwhenintegratedintoaPCIsystem.
WhenPCIEN=1,thePCImoduledisablestheinternalpullupandpulldownresistorsonthePCIpinsand
configurespinmultiplexingforPCI.PCIENisalsousedinbootmodeselectiontodifferentiatebetweenHPI
(PCIEN=0)andPCI(PCIEN=1)modes.ThePCIENinputmustbe0whentheEMIFAbootisselected
butneednotbe0forotherbootmodes.ThisallowsthedevicetobepartofaPCIsystemevenifbooted
fromUART,SPI,etc.
Seethedevice-specificdatamanualforPCIENpinmultiplexingdetailsinthepinmultiplexingcontrol0
register(PINMUX0).
118ResetSPRUEP9A–May2008
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