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Release 1.0, 1 July 2002 F. Chapter Contents vii
TLB Error Handling 195
Handling of TLB Entry Errors 195
Automatic Way Reduction of sTLB 196
Handling of Extended UPA Bus Interface Error 197
Handling of Extended UPA Address Bus Error 197
Handling of Extended UPA Data Bus Error 197
Q. Performance Instrumentation 201
Performance Monitor Overview 201
Sample Pseudocodes 201
Performance Monitor Description 203
Instruction Statistics 204
Trap-Related Statistics 206
MMU Event Counters 207
Cache Event Counters 208
UPA Event Counters 210
Miscellaneous Counters 211
R. UPA Programmer’s Model 213
Mapping of the CPU’s UPA Port Slave Area 213
UPA PortID Register 214
UPA Config Register 215
S. Summary of Differences between SPARC64 V and UltraSPARC-III 219
Bibliography 223
General References 223
Index 225