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41
F.CHAPTER
8
Memory Models
The SPARC V9 architecture is a model that specifies the behavior observable by
software on SPARC V9 systems. Therefore, access to memory can be implemented in
any manner, as long as the behavior observed by software conforms to that of the
models described in Chapter 8 of Commonality and defined in Appendix D, Formal
Specification of the Memory Models, also in Commonality.
The SPARC V9 architecture defines three different memory models: Total Store Order
(TSO), Partial Store Order (PSO), and Relaxed Memory Order (RMO). All SPARC V9
processors must provide Total Store Order (or a more strongly ordered model, for
example, Sequential Consistency) to ensure SPARC V8 compatibility.
Whether the PSO or RMO models are supported by SPARC V9 systems is
implementation dependent; SPARC64 V behaves in a manner that guarantees
adherence to whichever memory model is currently in effect
.
This chapter describes the following major SPARC64 V-specific details of memory
models.
■
SPARC V9 Memory Model on page 42
For general information, please see parallel subsections of Chapter 8 in
Commonality. For easier referencing, this chapter follows the organization of
Chapter 8 in Commonality, listing subsections whether or not there are
implementation-specific details.