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Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 89
8K_POINTER = TSB_Extension[63:14+N] 0 (VA[21+N:13] ⊕ TSB_Hash)
0000
64K_POINTER = TSB_Extension[63:14+N] 1
(VA[24+N:16] ⊕
TSB_Hash) 0000
Value of TSB_Hash for both a shared TSB and a split TSB
When 0 <= N <= 4,
TSB_Hash = context_register[N+8:0]
Otherwise, when 5 <= N <= 15,
TSB_Hash[ 12:0 ] = context_register[ 12:0 ]
TSB_Hash[ N+8:13 ] = 0 ( N-4 bits zero )
F.5 Faults and Traps
IMPL. DEP. #230
: The cause of a
data_access_exception
trap is implementation
dependent in JPS1, but there are several mandatory causes of
data_access_exception
trap.
SPARC64 V signals a
data_access_exception
for the causes, as defined in F.5 in
Commonality. However, caution is needed to deal with an invalid ASI. See
Section F.10.9 for details.
IMPL. DEP. #237
: Whether the fault status and/or address (DSFSR/DSFAR) are
captured when
mem_address_not_aligned
is generated during a JMPL or RETURN
instruction is implementation dependent.
On SPARC64 V, the fault status and address (DSFSR/DSFAR) are not captured
when a
mem_address_not_aligned
exception is generated during a JMPL or RETURN
instruction.
Additional information:
On SPARC64 V, the two precise traps—
instruction_access_error
and
data_access_error
—are recorded by the MMU in addition
to those in
TABLE
F-2 of Commonality. A modification (the two traps are added) of
that table is shown below.
TABLE F-2
MMU Trap Types, Causes, and Stored State Register Update Policy
Registers Updated
(Stored State in MMU)
Ref #Trap Name Trap Cause I-SFSR
I-MMU
Tag
Access
D-SFSR,
SFAR
D-MMU
Tag
Access Trap Type
1.
fast_instruction_access_MMU_miss
I-TLB miss X2 X 64
16
–67
16