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F.APPENDIX
125
M
Cache Organization
This appendix describes SPARC64 V cache organization in the following sections:
■
Cache Types on page 125
■
Cache Coherency Protocols on page 128
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Cache Control/Status Instructions on page 128
M.1 Cache Types
SPARC64 V has two levels of on-chip caches, with these characteristics:
■
Level-1 cache is split for instruction and data; level-2 cache is unified.
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Level-1 caches are virtually indexed, physically tagged (VIPT), and level-2 caches
are physically indexed, physically tagged (PIPT).
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All caches are 64 bytes in line size.
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All lines in the level-1 caches are included in the level-2 cache.
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Between level-1 caches, or level-1 and level-2 caches, coherency is maintained by
hardware. In other words,
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eviction of a cache line from a level-2 cache causes flush-and-invalidation of all
level-1 caches, and
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self-modification of an instruction stream modifies a level-1 data cache with
invalidation of a level-1 instruction cache.