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Release 1.0, 1 July 2002 F. Chapter C Implementation Dependencies 71
9 RDASR/WRASR privileged status
See A.50 and A.70 in Commonality for details of implementation-dependent
RDASR/WRASR instructions.
—
10–12 Reserved.
13 VER.impl
VER.impl =5 for the
SPARC64 V
processor.
20
14–15 Reserved. —
16 IU deferred-trap queue
SPARC64 V
neither has nor needs an IU deferred-trap queue.
24
17 Reserved. —
18 Nonstandard IEEE 754-1985 results
SPARC64 V
flushes denormal operands and results to zero when
FSR.NS = 1. For the treatment of denormalized numbers, please refer to
Section B.6, Floating-Point Nonstandard Mode, on page 61 for details.
18, 62
19 FPU version, FSR.ver
FSR.ver =0 for
SPARC64 V
.
18
20–21 Reserved.
22 FPU TEM, cexc, and aexc
SPARC64 V
implements all bits in the TEM, cexc, and aexc fields in
hardware.
19
23 Floating-point traps
In
SPARC64 V
floating-point traps are always precise; no FQ is needed.
24
24 FPU deferred-trap queue (FQ)
SPARC64 V
neither has nor needs a floating-point deferred-trap queue.
24
25 RDPR of FQ with nonexistent FQ
Attempting to execute an RDPR of the FQ causes an
illegal_instruction
exception.
24
26–28 Reserved. —
29 Address space identifier (ASI) definitions
The ASIs that are supported by
SPARC64 V
are defined in Appendix L,
Address Space Identifiers.
—
30 ASI address decoding
SPARC64 V
supports all of the listed ASIs.
117
31 Catastrophic error exceptions
SPARC64 V
contains a watchdog timer that times out after no instruction
has been committed for a specified number of cycles. If the timer times out,
the CPU tries to invoke an
async_data_error
trap. If the counter continues to
count to reach 2
33
, the processor enters error_state. Upon an entry to
error_state, the processor optionally generates a WDR reset to recover
from error_state.
138
TABLE C-1
SPARC64 V Implementation Dependencies (2 of 11)
Nbr SPARC64 V Implementation Notes Page