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22 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Performance Instrumentation Counter (PIC) Register (ASR
17)
The PIC register is implemented as described in SPARC JPS1 Commonality.
Four PICs are implemented in SPARC64 V. Each is accessed through ASR 17, using
PCR.SC as a select field. Read/write access to the PIC will access the PICU/PICL
counter pair selected by PCR. For PICU/PICL encodings of specific event counters,
see
Appendix Q, Performance Instrumentation
.
Counter Overflow.
On overflow, counters wrap to 0, SOFTINT register bit 15 is set,
and an interrupt level-15 exception is generated. The counter overflow trap is
triggered on the transition from value FFFF FFFF
16
to value 0. If multiple overflows
are generated simultaneously, then multiple overflow status bits will be set. If
overflow status bits are already set, then they remain set on counter overflow.
Overflow status bits are cleared by software writing 0 to the appropriate bit of
PCR.OVF and may be set by writing 1 to the appropriate bit. Setting these bits by
software does not generate a level 15 interrupt.
Dispatch Control Register (DCR) (ASR 18)
The DCR is not implemented in SPARC64 V. Zero is returned on read, and writes to
the register are ignored. The DCR is a privileged register; attempted access by
nonprivileged (user) code generates a
privileged_opcode
exception.
5.2.12 Registers Referenced Through ASIs
Data Cache Unit Control Register (DCUCR)
ASI 45
16
(ASI_DCU_CONTROL_REGISTER), VA = 0
16
.
The Data Cache Unit Control Register contains fields that control several memory-
related hardware functions. The functions include Instruction, Prefetch, write and
data caches, MMUs, and watchpoint setting. SPARC64 V implements most of
DCUCUR’s functions described in Section 5.2.12 of Commonality.
0 PRIV Defined in SPARC JPS1 Commonality, with the additional function of controlling PCR
accessibility as described above (impl. dep. #250).
TABLE 5-2
PCR
Bit Description (Continued)
Bit Field Description