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Release 1.0, 1 July 2002 F. Chapter 7 Traps 37
Although the standard behavior of the CPU upon an entry into error_state is to
internally generate a
watchdog_reset
(WDR), the CPU optionally stays halted upon an
entry to error_state depending on a setting in the OPSR register (impl. dep #40,
#254).
7.2 Trap Categories
Please refer to Section 7.2 of Commonality.
An exception or interrupt request can cause any of the following trap types:
■
Precise trap
■
Deferred trap
■
Disrupting trap
■
Reset trap
7.2.2 Deferred Traps
Please refer to Section 7.2.2 of Commonality.
SPARC64 V implements a deferred trap to signal certain error conditions (impl. dep.
#32). Please refer to the description of
I_UGE
error on “Relation between %tpc and
the instruction that caused the error” row in
TABLE P-2
(page 156) for details. See also
Instruction End-Method at ADE Trap on page 170.
7.2.4 Reset Traps
Please refer to Section 7.2.4 of Commonality.
In SPARC64 V, a watchdog reset (WDR) occurs when the processor has not
committed an instruction for 2
33
processor clocks.
7.2.5 Uses of the Trap Categories
Please refer to Section 7.2.5 of Commonality.
All exceptions that occur as the result of program execution are precise in
SPARC64 V (impl. dep. #33).
An exception caused after the initial access of a multiple-access load or store
instruction (LDD(A), STD(A), LDSTUB, CASA, CASXA, or SWAP) that causes a
catastrophic exception is precise in SPARC64 V.