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78 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
227 TSB number of entries
SPARC64 V
supports a maximum of 16 million entries in the common TSB
and a maximum of 32 million lines the Split TSB.
88
228 TSB_Hash supplied from TSB or context-ID register
TSB_Hash is generated from the context-ID register in
SPARC64 V
.
88
229 TSB_Base address generation
SPARC64 V
generates the TSB_Base address directly from the TLB
Extension Registers. By maintaining compatibility with UltraSPARC I/II,
SPARC64V provides mode flag MCNTL.JPS1_TSBP. When
MCNTL.JPS1_TSBP =0, the TSB_Base register is used.
88
230
data_access_exception
trap
SPARC64 generates
data_access_exception
only for the causes listed in
Section 7.6.1 of Commonality.
89
231 MMU physical address variability
SPARC64 V
supports both 41-bit and 43-bit physical address mode. The
initial width of the physical address is controlled by OPSR.
91
232 DCU Control Register CP and CV bits
SPARC64 V
does not implement CP and CV bits in the DCU Control
Register. See also impl. dep. #226.
23, 91
233 TSB_Hash field
SPARC64 V
does not implement TSB_Hash.
92
234 TLB replacement algorithm
For fTLB, SPARC64 V implements a pseudo-LRU. For sTLB, LRU is used.
93
235 TLB data access address assignment
The MMU TLB data-access address assignment and the purpose of the
address are implementation dependent.
94
236 TSB_Size field width
In
SPARC64 V
, TSB_Size is 4 bits wide, occupying bits 3:0 of the TSB
register. The maximum number of TSB entries is, therefore, 512 × 2
15
(16M
entries).
97
237 DSFAR/DSFSR for JMPL/RETURN
mem_address_not_aligned
A
mem_address_not_aligned
exception that occurs during a JMPL or RETURN
instruction does not update either the D-SFAR or D-SFSR register.
89, 97
238 TLB page offset for large page sizes
On
SPARC64 V
, even for a large page, written data for TLB Data Register is
preserved for bits representing an offset in a page, so the data previously
written is returned regardless of the page size.
87
239 Register access by ASIs 55
16
and 5D
16
In
SPARC64 V
, VA<63:19> of IMMU ASI 55
16
and DMMU ASI 5D
16
are
ignored. An access to virtual addresses 40000
16
to 60FF8
16
is treated as an
access 00000
16
to 20FF8
16
92
TABLE C-1
SPARC64 V Implementation Dependencies (9 of 11)
Nbr SPARC64 V Implementation Notes Page