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SPARC JPS1 Implementation Supplement:
Fujitsu SPARC64 V
• Release 1.0, 1 July 2002
P.3.2 Fatal Error Types
■
FE_UPA_ADDR_UNCORRECTED_ERROR — An uncorrected error in the
address received from UPA
■
FE_U2TAG_UNCORRECTED_ERROR — An uncorrected error detected in the U2
cache tag
■
FE_OTHER — A fatal error other than those listed above
P. 3 . 3 Ty p e s o f error_state Tr a ns i t i on Er ro rs
■
EE_TRAP_IN_MAXTL — A trap occurred while
TL
=
MAXTL
.
■
EE_SIR_IN_MAXTL — An SIR occurred while
TL
=
MAXTL
.
■
EE_SECOND_WATCH_DOG_TIMEOUT — A second watchdog timeout was
detected after an
async_data_error
exception with watchdog timeout indication
(first watchdog timeout) was generated.
■
EE_WATCH_DOG_TIMEOUT_IN_MAXTL — A watchdog timeout occurred
while
TL
=
MAXTL
.
■
EE_OPSR
—An uncorrectable error occurred in
OPSR
(Operation Status Register);
valid CPU operation after such an error cannot be guaranteed.
OPSR
is the
hardware mode-setting register.
OSPR
is not visible to software and is set by a
JTAG command.
■
EE_TRAP_ADDR_UNCORRECTED_ERROR
— When hardware calculated the
trap address to cause a trap, the valid address could not be obtained because of a
UE
in
ASI_TBA
, a
UE
in
%tt
, or a
UE
in the address calculator.
■
Other
error_state
transition errors:
■
Current SPARC64 V implementation
When hardware detects an
error_state
transition error other than those
described above, it causes a watchdog reset without setting any
EE_xxxx
bits in
ASI_STCHG_ERROR_INFO
.
9 EE_SIR_IN_MAXTL R Upon detection of the corresponding error, set to 1.
8 EE_TRAP_IN_MAXTL R Upon detection of the corresponding error, set to 1.
7:3 Reserved R Always 0.
2 FE_OTHER R Upon detection of the corresponding error, set to 1.
1 FE_U2TAG_UNCORRECTED_ERROR R Upon detection of the corresponding error, set to 1.
0 FE_UPA_ADDR_UNCORRECTED_ERROR RW Upon detection of the corresponding error, set to 1.
Writing 1 to this bit sets all fields in this register to 0.
TABLE P-10
Format of
ASI_STCHG_ERROR_INFO
Bit Description (Continued)
Bit Name RW Description