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SPARC JPS1 Implementation Supplement:
Fujitsu SPARC64 V
• Release 1.0, 1 July 2002
SPARC64 V Implementation and the Ideal Specification
In the table on page 183 (defining terminology in
TABLE P-20
), the rows (ASIs 6F
16
,
7F
16
, and EF
16
) with error type of “Not detected (#dv)” or “
COREERROR
(#dv)”
indicate that the SPARC64 V implementation deviates from the ideal specification,
which is described in
TABLE P-21
but is not implemented in SPARC64 V.
P.9 Cache Error Handling
In this section, handling of cache errors of the following types is specified:
■
Cache tag errors
■
Cache data errors in I1, D1, and U2 caches
This section concludes with the specification of automatic way reduction in the I1,
D1, and U2 caches.
P.9.1 Handling of a Cache Tag Error
Error in D1 Cache Tag and I1 Cache Tag
Both the D1 cache (Data level 1) and the I1 cache (Instruction level 1) maintain a
copy of their cache tags in the U2 (unified level 2) cache. The D1 cache tags, the D1
cache tags copy, the I1 cache tags, and the I1 cache tags copy are each protected by
parity.
TABLE P-21
Ideal Handling of ASI Register Errors (not implemented in SPARC64 V)
ASI VA
Register name RW
Error
Protect
Error Detect
Condition Error Type Correction
6F
16
— Parallel barrier assist RW Parity
AUG
always
LDXA
BV interface
(I)AUG_CRE
I(A)UG_CRE
(I)AUG_CRE
W
W
None
7F
16
40
16
-88
16
INTR_DATA0:7_R RECCLDXA
intr_receive
I(A)UG_CRE
BUSY
is set to 0
Interrupt
Receive
EF
16
— Parallel barrier assist RW Parity
AUG
always
LDXA
BV interface
(I)AUG_CRE
I(A)UG_CRE
(I)AUG_CRE
W
W
None