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SPARC JPS1 Implementation Supplement:
Fujitsu SPARC64 V
• Release 1.0, 1 July 2002
■
When a hardware unit first detects an uncorrected error in the cacheable data, the
hardware unit replaces the data and ECC of the cacheable data with a special
pattern that identifies the original error source and signifies that the data is
already marked.
The error marking helps identify the error source and prevent multiple error reports
by a single error even after several cache lines transfer with uncorrected data.
The following data are protected by the single-bit error correction and double-bit
error detection ECC code attached to every doubleword:
■
Main memory (DIMM)
■
UPA packet data containing cache line data and interrupt packet data
■
U2 (unified level 2) cache data
■
D1 cache data
■
The cacheable area block held by the channel
The ECC applied to these data is the ECC specified for UPA.
When the CPU and channel (U2P) detect an uncorrected error in the above cacheable
data that is not yet marked, the CPU and channel execute error marking for the data
block with an
UE
.
Whether the data with
UE
is marked or not is determined by the syndrome of the
doubleword data, as shown in
TABLE P-2
.
The syndrome 7F
16
indicates a 3-bit error in the specified location in the doubleword.
The error marking replaces the original data and ECC to the data and ECC, as
described in the following section. The probability of syndrome 7F
16
occurrence
other than the error marking is considered to be zero.
The Format of Error-Marking Data
When the raw
UE
is detected in the cacheable data doubleword, the erroneous
doubleword and its ECC are replaced in the data by error marking, as listed in
TABLE P-4
.
TABLE P-3
Syndrome for Data Marked for Error
Syndrome Error Marking Status Type of Uncorrected Error
7F
16
Marked Marked
UE
Multibit error pattern except for 7F
16
Not marked yet Raw
UE
TABLE P-4
Format of Error-Marked Data
Data/ECC Bit Value
data 63 Error bit. The value is unpredictable.
62:56 0 (7 bits).
55:42 ERROR_MARK_ID (14 bits).