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122 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
3. When the LBSY on the SB is changed, LBSY change information is broadcast to all
CPUs in the SB. Each CPU receives the change information and updates its copy.
4. On a read from an application, the copy value of LBSY, which is designated by
supervisor software, is returned.
High-Speed BST Write Mechanism
1. An application writes value, designated by supervisor software, to a BST.
2. The CPU sends BST write information to the system controller.
3. The system controller writes the BST.
A write to BST is faster than a noncacheable store.
L.4.2 ASI Registers
LBSY Control Register (
ASI_C_LBSYR0
,
ASI_C_LBSYR1
)
The LBSY control register designates which bit in the copy of LBSY is read through
ASI_LBSYRx.
[1] Register Name:
ASI_C_LBSYR0
,
ASI_C_LBSYR1
[2] ASI:
6F
16
[3] VA:
00
16
(
ASI_C_LBSYR0
),
08
16
(
ASI_C_LBSYR1
).
[4] RW Supervisor read/write
Bit Name RW Description
63 V RW Valid. When V =0, BL_num and SB_BPU_num are ignored
and a read to ASI_LBSYRx always returns 0. On V =1,
the copy value of LBSY selected by BL_num and
SB_BPU_num is read.
3 SB_BPU_num RW SB BPU relative number on the SB.
2:0 BL_num RW BL number in the selected SB BPU.