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Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 91
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An fDTLB entry parity error is detected in a fDTLB lookup for an instruction
operand access.
F.8 Reset, Disable, and RED_state Behavior
IMPL. DEP. #231
: The variability of the width of physical address is implementation
dependent in JPS1, and if variable, the initial width of the physical address after
reset is also implementation dependent in JPS1.
See impl. dep. #224 on page 86 for the variability of the width of physical address.
The physical address width to pass to the UPA interface is variable and is 43 bits
or 41 bits, as designated in UPA_configuration_register.AM field.
The initial value held in the external power-on reset sequencer is set to
UPA_configuraion_regiser.AM by the JTAG command during the power-on
reset sequence. So, the initial value of the UPA physical address width is system
dependent.
IMPL. DEP. #232
: Whether CP and CV bits exist in the DCU Control Register is
implementation dependent in JPS1.
On SPARC64 V, CP and CV bits do not exist in the DCU Control Register.
When DMMU is disabled, the processor behaves as if the TTE bits were set as:
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TTE.IE ← 0
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TTE.P ← 0
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TTE.W ← 1
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TTE.NFO← 0
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TTE.CV ← 0
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TTE.CP ← 0
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TTE.E ← 1
IMPL. DEP. #117
: Whether prefetch and nonfaulting loads always succeed when the
MMU is disabled is implementation dependent.
On SPARC64 V, the PREFETCH instruction completes without memory access
when the DMMU is disabled.
A data access exception is generated at the execution of the nonfaulting load
instruction when the DMMU is disabled, as defined in Section F.5 of
Commonality.