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F.APPENDIX
137
O
Reset, RED_state, and error_state
The appendix contains these sections:
■
Reset Types on page 137
■
RED_state and error_state on page 139
■
Processor State after Reset and in RED_state on page 141
O.1 Reset Types
This section describes the four reset types: power-on reset, watchdog reset,
externally initiated reset, and software-initiated reset.
O.1.1 Power-on Reset (POR)
For execution of the power-on reset on SPARC64 V, an external facility must issue
the required sequence of JTAG commands to the processor.
While the UPA_RESET_L pin is asserted (low) or the Power ready signal is
deasserted, the processor stops and executes only the specified JTAG command. The
processor does not change any software-visible resources in the processor except the
change by JTAG command execution and does not change any memory system state.
The sequence for the two types of power-on reset in SPARC64 V—hard power-on
reset and soft power-on reset—is described below.
1. The UPA_RESET_L pin is asserted (low). The processor stops.
2. The external facility issues the required sequence of the JTAG commands. A
different command sequence is required for hard power-on reset and soft power-
on reset. The external facility decides the POR reset type to be executed.