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40 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
■
Uncorrectable errors in the internal architecture registers (general registers–gr,
floating-point registers–fr, ASR, ASI registers)
■
Uncorrectable errors in the core pipeline
■
System data corruption
■
Watch dog timeout first time
■
TLB access error upon access by an ldxa or stxa instruction
Multiple errors may be reported in a single generation of the
async_data_error
exception. Depending on the situation, the
async_data_error
trap becomes a precise
trap, a disrupting trap, or a preemptive trap upon error detection. The TPC and
TNPC stacked by the exception may indicate the exact instruction, the preceding
instruction, or the subsequent instruction inducing the error. See Appendix P for
details of the
async_data_error
exception in SPARC64 V.