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138 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
3. The UPA_RESET_L pin is deasserted. The processor enters RED_state with
TT = 1 trap to RSTVaddr + 20
16
and starts the instruction execution.
O.1.2 Watchdog Reset (WDR)
The watchdog reset trap is generated internally in the following cases:
■
Second watchdog timeout detection while TL < MAXTL.
■
First watchdog timeout detection while TL = MAXTL
■
When a trap occurs while TL = MAXTL
When triggered by a watchdog timeout, a WDR trap has TT = 2 and control transfers
to RSTVaddr + 40
16
. Otherwise, the TT of the trap is preserved, causing an entry into
error_state.
O.1.3 Externally Initiated Reset (XIR)
The CPU has an externally initiated reset (XIR) pin named UPA_XIR_L (asserted
low). This pin must be asserted while the power supply is at full operational voltage
and the UPA clock is running.
The assertion of XIR generates a trap of TT = 3 and causes the processor to transfer
execution to RSTVaddr +60
16
and enter RED_state.
O.1.4 Software-Initiated Reset (SIR)
Any processor can initiate a software-initiated reset with an SIR instruction.
If TL (Trap Level) < MAXTL (5), an SIR instruction causes a trap of TT = 4 and causes
the processor to execute instructions from RSTVaddr +80
16
and enter RED_state.
If a processor executes an SIR instruction while TL =5, it enters error_state and
ultimately generates a watchdog reset trap.