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18 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
5.1.7 Floating-Point State Register (FSR)
Please refer to Section 5.1.7 of Commonality for the description of FSR.
The sections below describe SPARC64 V-specific features of the FSR register.
FSR_nonstandard_fp (NS)
SPARC V9 defines the FSR.NS bit which, when set to 1, causes the FPU to produce
implementation-dependent results that may not conform to IEEE Std 754-1985.
SPARC64 V implements this bit.
When FSR.NS = 1, denormal input operands and denormal results that would
otherwise trap are flushed to 0 of the same sign and an inexact exception is signalled
(that may be masked by FSR.TEM.NXM). See Section B.6, Floating-Point Nonstandard
Mode, on page 61 for details.
When FSR.NS = 0, the normal IEEE Std 754-1985 behavior is implemented.
FSR_version (
ver
)
For each SPARC V9 IU implementation (as identified by its VER.impl field), there
may be one or more FPU implementations or none. This field identifies the
particular FPU implementation present. For the first SPARC64 V, FSR.ver =0 (impl.
dep. #19); however, future versions of the architecture may set FSR.ver to other
values. Consult the SPARC64 V Data Sheet for the setting of FSR.ver for your
chipset.
FSR_floating-point_trap_type (
ftt
)
The complete conditions under which SPARC64 V triggers
fp_exception_other
with
trap type
unfinished_FPop
is described in Section B.6, Floating-Point Nonstandard Mode,
on page 61 (impl. dep. #248).
FSR_current_exception (cexc)
Bits 4 through 0 indicate that one or more IEEE_754 floating-point exceptions were
generated by the most recently executed FPop instruction. The absence of an
exception causes the corresponding bit to be cleared.
In SPARC64 V, the cexc bits are set according to the following pseudocode:
if (<LDFSR or LDXFSR commits>)
<update using data from LDFSR or LDXFSR>;
else if (<FPop commits with ftt = 0>)
<update using value from FPU>