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54 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
A.30 Load Quadword, Atomic [Physical]
The Load Quadword ASIs in this section are specific to SPARC64 V, as an extension
to SPARC JPS1.
Format (3) LDDA
Description
ASIs 34
16
and 3C
16
are used with the LDDA instruction to atomically read a 128-bit
data item, using physical addressing. The data are placed in an even/odd pair of 64-
bit registers. The lowest-address 64 bits are placed in the even-numbered register;
the highest-address 64 bits are placed in the odd-numbered register. The reference is
made from the nucleus context.
In addition to the usual traps for LDDA using a privileged ASI, a
data_access_exception
exception occurs for a noncacheable access or for the use of the
quadword-load ASIs with any instruction other than LDDA. A
mem_address_not_aligned
exception is generated if the access is not aligned on a 16-
byte boundary.
ASIs 34
16
and 3C
16
are supported in SPARC64 V in addition to those for Load
Quadword Atomic for virtually addressed data (ASIs 24
16
and 2C
16
).
The memory access for a load quad instruction with ASI_QUAD_LDD_PHYS{_L}
behaves as if the following TTE is set:
opcode imm_asi ASI value operation
LDDA ASI_QUAD_LDD_PHYS 34
16
128-bit atomic load, physically
addressed
LDDA ASI_QUAD_LDD_PHYS_L 3C
16
128-bit atomic load, little-endian,
physically addressed
Assembly Language Syntax
ldda [reg_addr] imm_asi, reg
rd
ldda [reg_plus_imm]
%asi
, reg
rd
31 24 02530 29 19 18 14 13 5 4
rd11 010011 simm_13rs1
i=1
rd11 010011 imm_asirs1 rs2
i=0