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SPARC JPS1 Implementation Supplement:
Fujitsu SPARC64 V
• Release 1.0, 1 July 2002
P. 4 . 2 A c t i o n o f async_data_error (
ADE
) Trap
The single-
ADE
trap and the multiple-
ADE
trap are generated upon the conditions
defined in
TABLE P-2
on page 154. The actions upon their occurrence are defined in
more detail in this section. For convenience, the shorthand
ADE
is used to refer to
async_data_error
.
1. Conditions that cause
ADE
trap:
An
ADE
trap occurs when one of the following conditions is satisfied:
■
When
ASI_ERROR_CONTROL.UGE_HANDLER
=0 and
I_UGE
s and/or
A_UGE
s are
detected, a single-
ADE
trap is generated.
■
When
ASI_ERROR_CONTROL.UGE_HANDLER
=1 and
I_UGEs
,
IAE
, and/or
DAE
are detected, a multiple-
ADE
trap is generated.
2. State change, trap target address calculation, and TL manipulation.
5:4 INSTEND R Trapped instruction end-method. Upon a single async_data_error trap
without watchdog timeout detection, INSTEND indicates the instruction end-
method of the trapped instruction pointed to by TPC as follows:
00
2
: Precise
01
2
: Retryable but not precise
10
2
: Reserved
11
2
: Not retryable
See Section P.4.3 for the instruction end-method for the
async_data_error
trap.
When a watchdog timeout is detected, the instruction end-method is
undefined.
3 PRIV R Privileged mode. Upon a single async_data_error trap, the PRIV field is set as
follows:
When the value of PSTATE.PRIV immediately before the single-
ADE
trap is
unknown because of an uncorrectable error in PSTATE, ASI_UGESR.PRIV is
set to 1. Otherwise, the value of PSTATE.PRIV immediately before the single-
ADE
trap is copied to ASI_UGESR.PRIV.
2 MUGE_DAE RMultiple
UGE
s caused by
DAE
. Upon a single-
ADE,
MUGE_DAE is set to 0. Upon
a multiple-
ADE
trap caused by a
DAE
, MUGE_DAE is set to 1. Upon a multiple-
ADE
trap not caused by a
DAE
,
MUGE_DAE
is unchanged.
1 MUGE_IAE RMultiple
UGE
s caused by
IAE
. Upon a single-
ADE
trap, MUGE_IAE is set to 0.
Upon a multiple-
ADE
trap caused by an
IAE
, MUGE_IAE is set to 1. Upon a
multiple-
ADE
trap not caused by an
IAE
,
MUGE_IAE
is unchanged.
0 MUGE_IUGE RMultiple
UGE
s caused by
I_UGE
. Upon a single-
ADE
trap, MUGE_IUGE is set to
0. Upon a multiple-
ADE
trap caused by an
I_UGE,
MUGE_IUGE is set to 1. Upon
a multiple-
ADE
trap not caused by an
I_UGE
,
MUGE_IUGE
is unchanged.
Other Reserved R Always 0.
TABLE P-11
ASI_UGESR
Bit Description (4 of 4)
Bit Name RW Description