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25
F.CHAPTER
6
Instructions
This chapter presents SPARC64 V implementation-specific instruction details and the
processor pipeline information in these subsections:
■
Instruction Execution on page 25
■
Instruction Formats and Fields on page 28
■
Instruction Categories on page 29
■
Processor Pipeline on page 31
For additional, general information, please see parallel subsections of Chapter 6 in
Commonality. For easy referencing, we follow the organization of Chapter 6 in
Commonality.
6.1 Instruction Execution
SPARC64 V is an advanced superscalar implementation of SPARC V9. Several
instructions may be issued and executed in parallel. Although SPARC64 V provides
serial program execution semantics, some of the implementation characteristics
described below are part of the architecture visible to software for correctness and
efficiency. The affected software includes optimizing compilers and supervisor code.
6.1.1 Data Prefetch
SPARC64 V employs speculative (out of program order) execution of instructions; in
most cases, the effect of these instructions can be undone if the speculation proves to
be incorrect.
1
However, exceptions can occur because of speculative data
prefetching. Formally, SPARC64 V employs the following rules regarding speculative
prefetching:
1. An async_data_error may be signalled during speculative data prefetching.