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80 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
252 DCUCR.DC (Data Cache Enable)
SPARC64 V
does not implement DCUCR.DC.
24
253 DCUCR.IC (Instruction Cache Enable)
SPARC64 V does not implement DCUCR.IC.
24
254 Means of exiting error_state
The standard behavior of a
SPARC64 V
CPU upon entry into
error_state is to reset itself by internally generating a
watchdog_reset
(WDR). However, OPSR can be set so that when error_state is entered, the
processor remains halted in error_state instead of generating a
watchdog_reset
.
37, 146
255
LDDFA with ASI E0
16
or E1
16
and misaligned destination register number
No exception is generated based on the destination register rd.
120
256
LDDFA with ASI E0
16
or E1
16
and misaligned memory address
For LDDFA with ASI E0
16
or E1
1
and a memory address aligned on a 2
n
-byte
boundary, a SPARC64 V processor behaves as follows:
n ≥ 3 (≥ 8-byte alignment): no exception related to memory address
alignment is generated.
n = 2 (4-byte alignment):
LDDF_mem_address_not_aligned
exception is
generated.
n ≤ 1 (≤ 2-byte alignment):
mem_address_not_aligned
exception is
generated.
120
257
LDDFA with ASI C0
16
–C5
16
or
C8
16
–
CD
16
and misaligned memory address
For LDDFA with C0
16
–
C5
16
or
C8
16
–
CD
16
and a memory address aligned on
a 2
n
-byte boundary, a SPARC64 V processor behaves as follows:
n ≥ 3 (≥ 8-byte alignment): no exception related to memory address
alignment is generated.
n = 2 (4-byte alignment):
LDDF_mem_address_not_aligned
exception is
generated.
n ≤ 1 (≤ 2-byte alignment):
mem_address_not_aligned
exception is
generated.
120
258
ASI_SERIAL_ID
SPARC64 V provides an identification code for each processor.
119
TABLE C-1
SPARC64 V Implementation Dependencies (11 of 11)
Nbr SPARC64 V Implementation Notes Page