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SPARC JPS1 Implementation Supplement:
Fujitsu SPARC64 V
• Release 1.0, 1 July 2002
Errors in registers other than those listed above and any errors in the TLB entry
remain.
b. Update of ASI_UGESR, as shown in
TABLE P-13.
c. Update of ASI_ERROR_CONTROL
Upon a single-
ADE
trap,
ASI_ERROR_CONTROL.UGE_HANDLER
is set to 1.
During the period after the single-
ADE
trap occurs and before a
RETRY
or
DONE
instruction is executed,
UGE_HANDLER
= 1 tells hardware that the urgent error
handler is running.
Upon a multiple
async_data_error
trap,
ASI_ERROR_CONTROL.WEAK_ED
is set
to 1 and the CPU starts running in the weak error detection state.
4. Set ASI_ERROR_CONTROL.UGE_HANDLER to 0.
Upon completion of a
RETRY
or
DONE
instruction,
ASI_ERROR_CONTROL.UGE_HANDLER
is set to 0.
P.4.3 Instruction End-Method at
ADE
Tra p
In SPARC64 V, upon occurrence of the
ADE
trap, the trapped instruction referenced
by
TPC
ends by using one of the following instruction end-methods:
■
Precise
■
Retryable but not precise (not included in JPS1)
■
Not retryable (not included in JPS1)
Upon a single-ADE trap, the trapped instruction end-method is indicated in
ASI_UGESR.INSTEND
.
TABLE P-13
ASI_UGESR
Update for Single and Multiple-
ADE
Exceptions
Bit Field Update upon a Single-ADE Trap Update upon a Multiple-ADE Traps
63:6 Error indication All bits in this field are updated.
All
I_UGE
s and
A_UGE
s detected at the
trap are indicated simultaneously.
Unchanged.
5:4 INSTEND The instruction end-method of the
instruction referenced by TPC is set.
Unchanged.
2 MUGE_DAE[ Set to 0. If the multiple-
ADE
trap was caused by a
DAE
,
MUGE_DAE
is set to 1.
Otherwise,
MUGE_DAE
is unchanged.
1 MUGE_IAE Set to 0. If the multiple-
ADE
trap was caused by
an
IAE
,
MUGE_IAE
is set to 1.
Otherwise,
MUGE_IAE
is unchanged.
0 MUGE_IUGE Set to 0. If the multiple-
ADE
trap was caused by
an
I_UGE
,
MUGE_IUGE
is set to 1.
Otherwise,
MUGE_IUGE
is unchanged.