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Release 1.0, 1 July 2002 F. Chapter C Implementation Dependencies 77
218
async_data_error
async_data_error
trap is implemented in
SPARC64 V
, using tt =40
16
. See
Appendix P for details.
39
219 Asynchronous Fault Address Register (
AFAR
) allocation
SPARC64 V
implements two AFARs:
• VA = 0 0
16
for an error occurring in D1 cache.
• VA = 0 8
16
for an error occurring in U2 cache.
177, 178
220 Addition of logging and control registers for error handling
SPARC64 V
implements various features for sustaining reliability. See
Appendix P for details.
—
221 Special/signalling ECCs
The method to generate “special” or “signalling” ECCs and whether
processor-ID is embedded into the data associated with special/signalling
ECCs is implementation dependent.
—
222 TLB organization
SPARC64 V has the following TLB organization:
• Level-2 micro ITLB (uITLB), 32-way fully associative
• Level-1 micro DTLB (uDTLB), 32-way fully associative
• Level-2 IMMU-TLB—consisting of sITLB (set-associative Instruction TLB)
and fITLB (fully associative Instruction TLB).
• Level-2 DMMU-TLB—consisting of sDTLB (set-associative Data TLB) and
fDTLB (fully associative Data TLB).
85
223 TLB multiple-hit detection
On SPARC64 V, TLB multiple hit detection is supported. However, the
multiple hit is not detected at every TLB reference. When the micro-TLB
(uTLB), which is the cache of sTLB and fTLB, matches the virtual address,
the multiple hit in sTLB and fTLB is not detected. The multiple hit is
detected only when the micro-TLB mismatches and the main TLB is
referenced.
86
224 MMU physical address width
The SPARC64 V MMU implements 43-bit physical addresses. The PA field of
the
TTE
holds a 43-bit physical address. Bits 46:43 of each TTE always read
as 0 and writes to them are ignored. The MMU translates virtual addresses
into 43-bit physical addresses. Each cache tag holds bits 42:6 of physical
addresses.
86
225 TLB locking of entries
In SPARC64 V, when a TTE with its lock bit set is written into TLB through
the Data In register, the TTE is automatically written into the corresponding
fully associative TLB and locked in the TLB. Otherwise, the TTE is written
into the corresponding sTLB of fTLB, depending on its page size.
87
226 TTE support for CV bit
SPARC64 V
does not support the CV bit in TTE. Since I1 and D1 are
virtually indexed caches, unaliasing is supported by
SPARC64 V
. See also
impl. dep. #232.
87
TABLE C-1
SPARC64 V Implementation Dependencies (8 of 11)
Nbr SPARC64 V Implementation Notes Page