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204 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Q.2.1 Instruction Statistics
Instruction statistics counters can be monitored by any SU or SL of any PIC.
●
Performance Monitor Cycle Count (cycle_counts)
Counts the cycles when the performance monitor is enabled. This counter is
similar to the %tick register but can separate user cycles from system cycles,
based on PCR.UT and PCR.ST selection.
001101 Reserved
001110 Reserved
001111 Reserved
010000 Reserved
010001 Reserved
010010 Reserved
010011 Reserved
010100 Reserved
010101 Reserved
010110 trap_all
trap_int_vector trap_int_level trap_spill trap_fill trap_trap_inst trap_IMMU
_miss
trap_DMMU
_miss
010111 Reserved
100000 Reserved
write_if_uTLB write_op_uTLB if_r_iu_req_mi
_go
op_r_iu_req
_mi_go
if_wait_all op_wait_all
100001 Reserved
100010 Reserved
100011 Reserved
110000 sx_miss
_wait_dm
sx_miss_wait
_pf
sx_miss_count
_dm
sx_miss_count_
pf
sx_read_count
_dm
sx_read_count
_pf
dvp_count_dm dvp_count_pf
110001 sreq_bi
_count
sreq_cpi_countsreq_cpb
_count
sreq_cpd_count upa_abus_busy upa_data_busyasi_rd_bar asi_wr_bar
110010 Reserved
110011 Reserved
111111 Disabled
Counter Any
Encoding 000000
2
TABLE Q-1
Events and Encoding of Performance Monitor (Continued)
Encoding
Counter
picu0 picl0 picu1 picl1 picu2 picl2 picu3 picl3