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24 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
Data Watchpoint Registers
No implementation-dependent feature of SPARC64 V reduces the reliability of data
watchpoints (impl. dep. #244).
SPARC64 V employs conservative check of PA/VA watchpoint over partial store
instruction. See Section A.42, Partial Store (VIS I), on page 57 for details.
Instruction Trap Register
SPARC64 V implements the Instruction Trap Register (impl. dep. #205).
In SPARC64 V, the least significant 11 bits (bits 10:0) of a CALL or branch (BPcc,
FBPfcc, Bicc, BPr) instruction in an instruction cache are identical to their
architectural encoding (as it appears in main memory) (impl. dep. #245).
5.2.13 Floating-Point Deferred-Trap Queue (FQ)
SPARC64 V does not contain a Floating-Point Deferred-trap Queue (impl. dep. #24).
An attempt to read FQ with an RDPR instruction generates an
illegal_instruction
exception (impl. dep. #25).
5.2.14 IU Deferred-Trap Queue
SPARC64 V neither has nor needs an IU deferred-trap queue (impl. dep. #16)
1 DC RW Not implemented in SPARC64 V (impl. dep. #252). It reads as 0 and writes to
it are ignored.
0 IC RW Not implemented in SPARC64 V (impl. dep. #253). It reads as 0 and writes to
it are ignored.
TABLE 5-3
DCUCR Description (Continued)
Bits Field Type Use — Description