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Release 1.0, 1 July 2002 F. Chapter 5 Registers 23
After a power-on reset (POR), all fields of DCUCR, including implementation-
dependent fields, are set to 0. After a WDR, XIR, or SIR reset, all fields of DCUCR,
including implementation-dependent fields, are set to 0.
The Data Cache Unit Control Register is illustrated in
FIGURE 5-2
and described in
TABLE 5-3
. In the table, bits are grouped by function rather than by strict bit sequence.
FIGURE 5-2
DCU Control Register Access Data Format (ASI 45
16
)
TABLE 5-3
DCUCR Description
Bits Field Type Use — Description
49:48 CP, CV RW Not implemented in SPARC64 V (impl. dep. #232). It reads as 0 and writes to
it are ignored.
47:42 impl. dep. Not used. It reads as 0 and writes to it are ignored.
41 WEAK_SPCA RW Used for disabling speculative memory access (impl. dep. #240). When
DCUCR.WEAK_SPCA = 1, the branch history table is cleared and no longer
issues aggressive instruction prefetch.
During DCUCR.WEAK_SPCA = 1, aggressive instruction prefetching is
disabled and any load and store instructions are considered presync
instructions that are executed when all previous instructions are committed.
Because all CTI are considered as not taken, instructions residing beyond 1
Kbyte of a CTI may be fetched and executed.
On entering aggressive instruction Prefetch disable mode, supervisor
software should issue membar #Sync, to make sure all in-flight instructions
in the pipeline are discarded.
During DCUCR.WEAK_SPCA = 1, an L2 cache flush by writing 1 to
ASI_L2_CTRL.U2_FLUSH remains pending internally until
DCUCR.WEAK_SPCA is set to 0. To wait for completion of the cache flush, a
member #Sync must be issued after DCUCR.WEAK_SPCA is set to 0.
Executing a membar #Sync while the DCUCR.WEAK_SPCA = 1 after writing 1
to ASI_L2_CTRL.U2_FLUSH does not wait for the cache flush to complete.
40:33 PM<7:0> Defined in SPARC JPS1 Commonality.
32:25 VM<7:0> Defined in SPARC JPS1 Commonality.
24, 23 PR, PW Defined in SPARC JPS1 Commonality.
22, 21 VR, VW Defined in SPARC JPS1 Commonality.
20:4 — Reserved.
3 DM Defined in SPARC JPS1 Commonality.
2 IM Defined in SPARC JPS1 Commonality.
Implementation dependent PM VM PR PW VR DM 0
012342122234042 20
VW
2425323347
IM 0
0
4849
0
5063
—
—
WEAK_SPCA
41