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Release 1.0, 1 July 2002 F. Chapter A Instruction Definitions: SPARC64 V Extensions 57
A.42 Partial Store (VIS I)
Please refer A.42 in Commonality for general details.
Watchpoint exceptions on partial store instructions occur conservatively on
SPARC64 V. The DCUCR Data Watchpoint masks are only checked for nonzero value
(watchpoint enabled). The byte store mask (r[rs2]) in the partial store instruction
is ignored, and a watchpoint exception can occur even if the mask is zero (that is, no
store will take place) (impl. dep. #249).
For a partial store instruction with mask = 0, SPARC64 V still issues a UPA
transaction with zero-byte mask.
Exceptions: fp_disabled
PA_watchpoint
VA_watchpoint
illegal_instruction
(misaligned rd)
mem_address_not_aligned
(see Partial Store ASIs on page 120)
data_access_exception
(see Partial Store ASIs on page 120)
LDDF_mem_address_not_aligned
(see Partial Store ASIs on page 120)
data_access_error
fast_data_access_MMU_miss
fast_data_access_protection
A.49 Prefetch Data
Please refer to Section A.49, Prefetch Data, of
Commonality for principal information.
The prefetcha instruction of SPARC64 V works for the following ASIs.
■
ASI_PRIMARY (080
16
), ASI_PRIMARY_LITTLE (088
16
)
■
ASI_SECONDARY (081
16
), ASI_SECONDARY_LITTLE (089
16
)
■
ASI_NUCLEUS (04
16
), ASI_NUCLEUS_LITTLE (0C
16
)
■
ASI_PRIMARY_AS_IF_USER (010
16
), ASI_PRIMARY_AS_IF_USER_LITTLE
(018
16
)
■
ASI_SECONDARY_AS_IF_USER (011
16
), ASI_SECONDARY_AS_IF_USER_LITTLE
( 019
16
)
If an ASI other than the above is specified, prefetcha is executed as a nop.