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Release 1.0, 1 July 2002 F. Chapter P Error Handling
169
The following actions are executed in this order:
a. State transition
if (
TL
=
MAXTL
), the CPU enters
error_state
and abandons the
ADE
trap;
else if (CPU is in execution state && (
TL
=
MAXTL
−
1)), then the CPU enters
RED_state
.
b. Trap target address calculation
When the CPU is in execution state, trap target address is calculated by
%tba
,
%tt
, and
%tl
.
Otherwise, the CPU is in
RED_state
and the trap target address is set to
RSTVaddr
+A0
16
.
c. TL is incremented: TL ← TL +1.
3. Save the old value into TSTATE, TPC, and TNPC.
PSTATE
,
PC
, and
NPC
immediately before the
ADE
trap are copied into
TSTATE
,
TPC
, and
TNPC
, respectively. If the copy source register contains an uncorrectable
error, the copy target register also contains the
UE
.
4. Set the specific register setting:
The following three sets of registers are updated:
a. Update and validation of specific registers.
Hardware writes the registers listed in
TABLE P-12
.
The error(s) in a written register are removed by setting the correct value to the
error checking (parity) code during the full write of the register.
TABLE P-12
Registers Written for Update and Validation
Register Condition For Writing Value Written
PSTATE Always AG =1, MG=0, IG =0, IE =0, PRIV =1, AM =0, PEF =1,
RED = 0 (or 1 depending on the CPU status), MM = 00, TLE =0,
CLE =0.
PC Always
ADE
trap address.
nPC Always
ADE
trap address + 4.
CCR When the register contains
UE
0.
FSR, GSR When the register contains
UE
If either FSR or GSR contains a
UE
, 0 is written to that
register. When 0 is written to FSR and/or GSR upon a single-
ADE
trap, ASI_UGESR.IUG_%F is set to 1.
CWP, CANSAVE,
CANRESTORE,
OTHERWIN,
CLEANWIN
When the register contains
UE
Any register among CWP, CANSAVE, CANRESTORE,
OTHERWIN, and CLEANWIN that contains a UE is written to 0.
When 0 is written to one of these registers upon a single-
ADE
trap, ASI_UGESR.IUG_PSTATE =1 is set to 1.