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238 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
store order (STO)75
TSO41
,
42
MEMORY_CONTROL register186
mmask field56
MMU
disabled91
event counting207
exceptions recorded89
Memory Control Register92
physical address width86
registers accessed92
TLB data access address assignment94
TLB organization85
MOESI cache-coherence protocol128
Multiply Add/Subtract instructions53
N
noncacheable access54
,
126
nonleaf routine53
nonspeculative distribution10
nonstandard floating-point (NS) field of FSR register18
,
71
nonstandard floating-point mode18
,
62
O
OBP
facilitating diagnostics126
notification of error163
resetting WEAK_ED150
validating register error handling181
with urgent error151
Operating Status Register (OPSR)37
,
140
,
216
,
221
OTHERWIN register75
,
166
out-of-order execution25
P
panic process152
parallel barrier assist187
,
188
parity error
counting in D1 cache193
D1 cache tag189
fDTLB lookup91
I1 cache data190
I1 cache tag189