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17
F.CHAPTER
5
Registers
The SPARC64 V processor includes two types of registers: general-purpose—that is,
working, data, control/status—and ASI registers.
The SPARC V9 architecture also defines two implementation-dependent registers:
the IU Deferred-Trap Queue and the Floating-Point Deferred-Trap Queue (FQ);
SPARC64 V does not need or contain either queue. All processor traps caused by
instruction execution are precise, and there are several disrupting traps caused by
asynchronous events, such as interrupts, asynchronous error conditions, and
RED_state entry traps.
For general information, please see parallel subsections of Chapter 5 in
Commonality. For easier referencing, this chapter follows the organization of
Chapter 5 in Commonality.
For information on MMU registers, please refer to Section F.10, Internal Registers and
ASI operations, on page 92.
The chapter contains these sections:
■
Nonprivileged Registers on page 17
■
Privileged Registers on page 19
5.1 Nonprivileged Registers
Most of the definitions for the registers are as described in the corresponding
sections of Commonality. Only SPARC64 V-specific features are described in this
section.