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Release 1.0, 1 July 2002 F. Chapter F Memory Management Unit 87
The physical address length to be passed to the UPA interface is 41 bits or 43 bits,
as designated in the
ASI_UPA_CONFIG.AM
field. When the 41-bit
PA
is specified
in
ASI_UPA_CONFIG.AM
, the most significant 2 bits of the CPU internal physical
address are discarded and only the remaining least significant 41 bits are passed
to the UPA address bus. If the discarded most significant 2 bits are not 0, the
urgent error
ASI_UGESR.SDC
is detected after the invalid address transfer to the
UPA interface. Otherwise, when the 43-bit PA is specified in
ASI_UPA_CONFIG.AM,
the entire 43 bits of CPU internal physical address are
passed to the UPA address bus.
IMPL. DEP. #238
:
When page offset bits for larger page size (
PA
<15:13>,
PA
<18:13>,
and
PA
<21:13> for 64-Kbyte, 512-Kbyte, and 4-Mbyte pages, respectively) are stored
in the TLB, it is implementation dependent whether the data returned from those
fields by a Data Access read are zero or the data previously written to them.
On SPARC64 V, the data returned from
PA
<15:13>,
PA
<18:13>, and
PA
<21:13> for
64-Kbyte, 512-Kbyte, and 4-Mbyte pages, respectively, by a Data Access read are
the data previously written to them.
IMPL. DEP. #225
:
The mechanism by which entries in TLB are locked is
implementation dependent in JPS1.
In SPARC64 V, when a TTE with its lock bit set is written into TLB through the
Data In register, the TTE is automatically written into the corresponding fully
associative TLB and locked in the TLB. Otherwise, the TTE is written into the
corresponding sTLB or fTLB, depending on its page size.
IMPL. DEP. #242
:
An implementation containing multiple TLBs may implement the
L
(lock) bit in all TLBs but is only required to implement a lock bit in one TLB for each
page size. If the lock bit is not implemented in a particular TLB, it is read as 0 and
writes to it are ignored.
In SPARC64 V, only the fITLB and the fDTLB support the lock bit as described in
TABLE F-1
. The lock bit in sITLB and sDTLB is read as 0 and writes to it are
ignored.
IMPL. DEP. #226
:
Whether the
CV
bit is supported in
TTE
is implementation
dependent in JPS1. When the
CV
bit in
TTE
is not provided and the implementation
has virtually indexed caches, the implementation should support hardware
unaliasing for the caches.
In SPARC64 V, no TLB supports the
CV
bit in
TTE
. SPARC64 V supports hardware
unaliasing for the caches. The
CV
bit in any
TLB
entry is read as 0 and writes to it
are ignored.