Filter
Top Products
8 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
1.3.5 Secondary Cache and External Access Unit (SXU)
The SXU controls the operation of unified level-2 caches and the external data access
interface (extended UPA interface).
TABLE 1-4
describes the major blocks of the SXU.
TABLE 1-4
Secondary Cache and External Access Unit Major Blocks
Name Description
Unified level-2 cache 2-Mbyte, 4-way associative, 64-byte line, writeback; provides low
latency data source for both instruction level-1 cache and data
level-1 cache.
Movein buffer Sixteen entries, 64-bytes/entry; catches returning data from
memory system in response to the cache line read request. A
maximum of 16 outstanding cache read operations can be issued.
Moveout buffer Eight entries, 64-bytes/entry; holds writeback data. A maximum
of 8 outstanding writeback requests can be issued.
Extended UPA interface
control logic
Send/receive transaction packets to/from Extended UPA
interface connected to the system.