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202 SPARC JPS1 Implementation Supplement: Fujitsu SPARC64 V • Release 1.0, 1 July 2002
/* clear pics without altering sl/su values */
pic_init = 0x0;
pcr = rd_pcr();
pcr.ulro = 0x1; /* don’t change su/sl on write */
pcr.ovf = 0x0; /* clear overflow bits also */
pcr.ut = 0x0;
pcr.st = 0x0; /* disable counts for good measure */
for (i=0; i<=pcr.nc; i++) {
/* select the pic to be written */
pcr.sc = i;
wr_pcr(pcr);
wr_pic(pic_init);/* clear pic i */
}
Counter Event Selection and Start
Counter events are selected through PCR.SC and PCR.SU/PCR.SL fields. The
following pseudocode selects events and enables counters (assuming privileged
access):
pcr.ut = 0x0; /* initially disable user counts */
pcr.st = 0x0; /* initially disable system counts */
pcr.ulro = 0x0; /* make sure read-only disabled */
pcr.ovro = 0x1; /* do not modify overflow bits */
/* select the events without enabling counters */
for(i=0; i<=pcr.nc; i++) {
pcr.sc = i;
pcr.sl = select an event;
pcr.su = select an event;
wr_pcr(pcr);
}
/* start counting */
pcr.ut = 0x1;
pcr.st = 0x1;
pcr.ulro = 0x1; /* for not changing the last su/sl */
/* resetting of overflow bits can be done here */
wr_pcr(pcr);
Counter Stop and Read
The following pseudocode disables and reads counters (assuming privileged
access):
pcr.ut = 0x0; /* disable counts */
pcr.st = 0x0; /* disable counts */
pcr.ulro = 0x1; /* enable sl/su read-only */
pcr.ovro = 0x1; /* do not modify overflow bits */