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Release 1.0, 1 July 2002 F. Chapter R UPA Programmer’s Model 217
29:23 PCON Processor Configuration. Separated into PCON<6:4> and PCON<3:0>.
PCON<6:4> (UPA_CONFIG<29:27>) represents the size of class 1 request queue in the
System Controller (SC).
000
2
:1
001
2
– 010
2
:
1,
but should not be specified for the extension
011
2
:4
100
2
– 110
2
: 4, but should not be specified for the extension
111
2
:8
PCON<3:0> (UPA_CONFIG<26:23> represents the size of class 0 request queue in the
System Controller (SC).
0000
2
:1
0001
2
– 0010
2
:
1,
but should not be specified for the extension
0011
2
:4
0100
2
– 1110
2
:4, but should not be specified for the extension
1111
2
:16
22 UPC_CAP2 This field is connected to the UPA’ Port ID register bit 35, SREQ_S field
21:17 MID Module (Processor) ID register. Identifies the unique processor ID. This value is loaded
from the UPA_MasterID<4:0> pins.
16:0 UPC_CAP This field is a composite of the following fields in the UPA’ Port ID register.
16:15 PINT_RDQ
14:9 PREQ_DQ
8:5 PREQ_RQ
4:0 UPA_CAP
TABLE R-3
UPA Config Register Description (Continued)
Bits Field Description