Filter
Top Products
Release 1.0, 1 July 2002 F. Chapter P Error Handling
175
■
If the
Prio_U2
column for the error shown in the table row is blank, the error is
never recorded into
ASI_AFAR_U2
.
■
Otherwise, the
Prio_U2
column for the error shown in the table row indicates
the
ASI_AFAR_U2
recording priority, as follows. Let
P_U2
be the
Prio_U2
column value for the error
E2
. Then:
Upon detection of the error
E2
, if
P_U2
>
ASI_AFAR_U2.CONTENTS
, the error
E2
is recorded into
ASI_AFAR_U2
and
ASI_AFAR_U2.CONTENTS
is set
to
P_U2
.
Upon detection of the error
E2
, if P_U2
≤ ASI_AFAR_U2.CONTENTS
, the error
E2
is not recorded in
ASI_AFAR_U2
and
ASI_AFAR_U2
is unchanged.
TABLE P-15
ASI_ASYNC_FAULT_STATUS
Bit Description
Bit Name R/W Prio_D1 Prio_U2 Description
Bits 10:0 are restrainable error-pending “sticky” bits. Each bit in
ASI_AFSR
<10:0> is set to 1 when the
corresponding error is detected. The only way each of these error sticky bits can be cleared is to write 1 to it.
When 1 is held in a bit of
ASI_AFSR
and the trap disable condition specified in the
TABLE P-2
is not satisfied,
an ECC_error trap is generated.
10 DG_L1$U2$STLB RW1C Degradation in L1$, U2$, and sTLB. This bit is set
when automatic way reduction is applied in I1$,
D1$, U2$, sITLB, or sDTLB. See Section P.9.5 and
Section P.10.2 for further details about when this bit
is set.
9 CE_INCOMED RW1C 40
16
Correctable error in incoming data from the UPA bus.
CE
is detected in the following cases:
• U2 (unified level 2) cache fill
• Data read from noncacheable area
The two cases can be separated by the physical
address indicated in ASI_AFAR_U2. For U2 cache fill,
normally the
CE
in DIMM is detected.
Programming Note: Data is transferred on the UPA
bus in units of 16 bytes (one quadword). For data
read from a noncacheable area, a correctable error in
the opposite doubleword from the one that was
accessed by the instruction may be reported as
CE_INCOMED
.
The address indicated in ASI_AFAR_U2 for
CE_INCOMED always has doubleword resolution and
indicates the correct error location for the incoming
data path. However, the error reported for the
noncacheable area read may be for the opposite
doubleword in a quadword from the doubleword
accessed by the instruction.